David Levy
Karyatidon st., 9, Apt- Larnaca, Cyprus
Mobile: -
e-mail:-LinkedIn: https://www.linkedin.com/in/david-levy-phd/
Curriculum Vitae
Professional profile
Senior ASIC Architect, System Engineer, HW/SW Partitioning, Senior ASIC Designer, DSP
algorithms implementation. Extensive knowledge in wired and wireless communication lower
layers in Telecommunication and Automotive domains.
Personal details
Nationalities: French and Israeli
Studies-: PhD in Applied Informatics at Slovak University of Technology (STU) in Bratislava,
Slovakia. Thesis title: “WLAN Power Save by Header Compression and Packet Overhearing
Reduction”.
Supervisor: Prof. Ivan Kotuliak (Slovak University of Technology, Bratislava)
Reviewers: Prof. Markus Rupp (Vienna University of Technology, Austria), Prof. Martin Klimo
(University of Zilina, Slovakia-: Master in Electronics Engineering at Université Libre de Bruxelles (ULB) in
Brussels, Belgium. Honored degree.
Experience
Now-2023: Senior ASIC Architect and Designer at Braiins (Czech Republic), remote work.
Architecture, implementation in RTL and verification in System-Verilog and Python of a Hash
SHA-256 Machine Cluster-: Senior ASIC Architect and Designer at Bitec in Marbella (Spain), remote work.
Architecture, implementation in RTL and verification in System-Verilog of video image
compression standard DSC-: Senior ASIC Architect at CEVA in Herzliya (Israel).
I wrote all Verilog code for all the blocks and DSP extensions mentioned below. I mentored two
students to help with verification. I defined the verification plan for all blocks and wrote all
specifications.
Channel State Information for LTE:
● HW architecture of Neural Network for Mean MIB function approximation
● HW architecture of DSP extensions: QR matrix decomposition, Log2 approximation,
Binary Search
Internet of Things for LTE (Category M):
● HW/SW partitioning for Viterbi decoder, Turbo code encoder and uplink rate matching
● SW architecture for uplink rate matching
● HW architecture of DSP extensions for AES ciphering, Viterbi ACS and Traceback,
Turbo code interleaver and convolutional encoder, Rate matching basic functions:
shuffle, transpose and permute-: Concept Engineer at Infineon in Villach (Austria).
Coordinator between the different team members: digital and analog designers, verification and
test engineers, project manager and functional safety engineer.
Architecture and microarchitecture specification, HW/FW partitioning of a Magnetic Sensor
digital part.
Architecture specification, HW/FW partitioning of combined PSI5 and DSI3 receivers. Matlab
models of threshold adaptation algorithm and symbol decoding algorithm based on correlation.
Architecture specification, HW/FW partitioning of an event verification controller IP in an
Airbag controller chip.
Development following the ISO26262 process for a HW component-: System Architect at Texas Instruments in Raanana (Israel).
WLAN IP architecture specification for 3 product generations. WLAN related features
specification improving both power and reach involving both HW and SW. WiFi Alliance
member and contributor-: Hardware System Architect at Seabridge (Siemens) in Hod HaSharon-: STMicroelectronics in Belgium
∙
ASIC project leader (5 designers): ADSL chip improvement.
∙
Viterbi decoder & error correction decoder algorithms analysis, improvement,
implementation in VHDL and synthesis.
∙
System architecture specification and design follow-up of an ADSL TC IP with an
embedded ARM-: ASIC design at Infineon Tel-Aviv. VHDL Design, testing, integration and synthesis
of ADSL and ATM functional units for an ADSL digital chip with 2 embedded DSP’s-: Nbase Communications in Israel. Board designer, Transceivers for Ethernet 100Mb/s
and Switch for Ethernet 10Mb/s. Technical support engineer for Europe-: Last year Project: simulation and comparison of communication protocols (Aloha,
polling and TDMA). The study was done in Brussels, Belgium.
Languages
Human languages: Fluent in French, English and Hebrew. Conversational German. Basic
Spanish.
Software languages: C, Matlab, Python and Assembler.
Hardware languages: Verilog and VHDL
Patents
2016: Walsh Encoding for Peripheral Sensor Interface 5 (US Patent 9,647,-: Clockless Serial Slave Device (US Patent 9,582,-: Bus Architecture and Access Method for Plastic Waveguide (US Patent 9,712,-: Sensor Systems and Methods Utilizing Adaptively Selected Carrier Frequencies (US
Patent 9,529,763)
2014: Symbol decoder, threshold estimation and correlation systems and methods (US Patent
8,842,-: Methods and Apparatus to locate a Wireless Device (US Patent 8,164,515)
Publications
2015: D. Levy, I. Kotuliak, “WLAN Power Saving Using Packet Overhearing Reduction”,
Telecommunication Systems Journal (Springer), DOI: 10.1007/s--y.
2014: D. Levy, “Reduced power consumption by randomization for DSI3”, International
Conference on Communication Systems, Networks and Digital Signal Processing, Vol. 2, No. 1.
2014: D. Levy, I. Kotuliak, P. Truchly, “WLAN Performance Improvement by Header
Compression and Packet Overhearing Reduction”, Journal of Electrical Engineering (JEEEC),
Vol. 65, No. 4, pp-: D. Levy, “DSI3 Sensor to Master Decoder using Symbol Pattern Recognition”, SAE Int. J.
Passeng. Cars & Electron. Electr. Syst., April, 1st,-: D. Levy, “DSI3 Sensor to Master Current Threshold Adaptation for Pattern Recognition”,
International Journal of Signal Processing Systems, Vol. 1, No. 2, pp. 141-145, December.
Received the Excellent Paper Award.
2013: D. Levy, I. Kotuliak, “General all-Layers combined with Efficient WLAN MAC Layer
Headers Compression”, Proceedings of International Conference on Advances in Mobile
Computing and Multimedia, December 2-4.
2012: D. Levy, I. Kotuliak, “WLAN power consumption analytical model”, Wireless and Mobile
Networking Conference, September 19-21.
