David Levy

I translate any kind of requirement, be it textual, high level coding language (C/C++/Python/Matlab), or schematic to synthesizable clear and structured Verilog or VHDL code. I will build testbench environment for the design as well. The code will be optimized for minimum resource usage, latency or power consumption, upon prioritization.

I have experience in different roles in Hardware: Senior ASIC Architect, System Engineer, HW/SW Partitioning, Senior ASIC Designer, DSP algorithms implementation in VHDL/Verilog.

I have extensive knowledge in wired and wireless communication lower layers in Telecommunication and Automotive domains.