Sayandip Kar

Sayandip Kar AF-199 Rabindrapally Krishnapur Kolkata 700101  (- | - |  https://www.linkedin.com/in/sayandipkar Education Indraprastha Institute of Information Technology (IIIT) Delhi, India MASTER OF TECHNOLOGY IN VLSI AND EMBEDDED SYSTEMS July 2019 - June 2021 • CGPA: 8.44/10 • Courses: Digital VLSI Design, Advanced Embedded Logic Design, Memory Design and Testing and VLSI Design Flow among others Heritage Institute of Technology Kolkata, India BACHELOR OF ENGINEERING IN ELECTRONICS AND COMMUNICATION SYSTEMS Aug 2014 - May 2018 • CGPA: 8.94/10 South Point High School CLASS 12 (W.B.C.H.S.E) Kolkata, India Year of Passing: June 2014 • Percentage: 85 Skills Languages Technologies Tools Technical Electives Verilog, C 65nm and 180nm Vivado, Virtuoso, Incisive, Genus, Tempus, Conformal, Encounter Digital Hardware Design, Integrated Circuit Fabrication, Solid State Devices Experience TEJAS NETWORKS HARDWARE ENGINEER INTERN Bangalore, India January 2021 - June 2021 • Explored PCB development flow and physical designs in Allegro Physical Viewer. • Underwent training on different Tejas products like TJ1400 and TJ1600 and technologies like GPON, OTN, etc Academic Projects A 585mV, 16.6fJ/cycle, 0.2֐W Variation Tolerant Scannable Hybrid Flip-Flop in 65nm CMOS LSTP Designed an energy efficient hybrid flip-flop capable of operating at near-threshold voltages and enabling time borrowing capabilities to mitigate data-path variations. It showed superior performance and PDP compared to static flip-flops like TGFF and S2CFF. Studying Variations at Near-Threshold Voltages Design a soft-edged flip flop and used it at a system level to mitigate variations at NTV, STV and nominal operating voltages. Comapred the improvement in variations in each voltage domain. RTL to GDSII Flow Using Cadence Tools Benchmarked a given specification and carried out simulation, synthesis, STA, Equivalence Checking, DFT and physical design. A StrongArm Type Sense Amplifier Designed a Strong-Arm type sense amplifier to be used as a peripheral device for an SRAM and completed the common centroid layout. Strong-Arm sense amplifiers enable low power operation. Review Paper on Post Silicon Validation and Challenges Studied about various DFT architectures, trace methods and analyzed advantages and consequences that each of them present. AOI 221 Using PTL Designed and benchmarked an AOI 221 circuit using Pass Transistor Logic, completed the layout and performed the post-layout analysis (RC extraction). Achievements and Certificates 2012 Diploma, Fine Arts and Painting 2013 Swimmer, Bidhan Nagar Swimming Association 2021 Cadence Certified Professional, Verilog, Advanced Synthesis with Genus and STA 2021 Certificant, The Science of Well Being Chandigarh, India Kolkata, India N.A Yale University