Hemasree Midde

Professional Summary 1 + Year of experience in System on Chip Verification with a solid understanding of Designing and Test bench Design and its Execution. Professional Responsibilities Experience in Functional testing. Hands on experience in preparing test automation scripts using UVM and Perl Scripting. Ability to learn quickly and be productive in new areas. Professional Experience Worked as a Design Verification intern in Sion Semiconductors Pvt. Ltd,Hyderabad from Dec 2019 to Dec 2020. Presently working as Design Engineer in DataPoint info solutions. Skill Summary Core Skills : Verilog, SV, UVM, Perl Scripting , C ,C++ Testing tools : Xilinx ISim(ISE), multisim Backend tool : Tanner EDA Operating Systems : Windows10, LINUX Academic Qualifications B. Tech(Electronics and Communication Engineering) from Vikas College of Engineering and Technology with 81 percent. Project Profile Project 1 : SMART NEOPIXEL BOARD Description : A neopixel board which displays our speech from anywhere by making use of IOT and the processing of speech data done by making use of Arduino. Responsibilities: In this project I did coding for the Arduino using embedded C. Project 2 : I2C Description : It is a serial communication protocol and it is widely used for attaching lower –speed peripherals ICs to process and microcontrollers in short-distance,intraboard communication . Responsibilities: I designed this protocol and validate its features using various test cases. Project 3 : SPI Description : A synchronous serial communication protocol used for short-distance communication and its typical application include secure digital cards and LCDs. Project 4 : UART Description : Universal asynchronous receiver-transmitter for asynchronous serial communication and in which the data format and transmission speeds are configurable. Responsibilities: I wrote testbench by making use of UVM and validate its functionality. Project 5 : AMBA AXI and ACE Description : Designing this protocol and its testing gave an idea of connection and management of functional blocks in multi-processor Design with bus architecture. Responsibilities: Designing these two protocols and their testing using UVM test bench.