Polu Giridhar Reddy
(--
Objective
In anticipation of an opportunity providing intellectually challenging work in the field of Electronics for proving and enriching my knowledge and skills.
Education
Indian Institute of Technology (IIT BHU), Varanasi-
B. Tech. in Electronics Engineering (CGPA 9.09 absolute scale)
Good Shepherd School
2008
Secondary School Certificate Examination (Percentage: 93.00%)
Narayana Junior College
2010
Board Of Intermediate, A.P (Percentage: 97.90%)
Skills And Interests
Languages: Verilog HDL, C
Tools used: Xilinx ISE, ADS and Hyper Lynx for Signal integrity, Cadence Allegro
Areas of Interest: Digital design.
Current Full time work Centre For Development Of Telematics (CDOT) Aug2014 - Present
Working as a Research Engineer in the field of Router hardware.
Worked at various levels of Board design for the Node cards of Terabit Router.
Architecture planning based on the customer requirements and specifications.
Design of the entire board including the component selection, schematics, layout and Routing.
Programmable devices selection and logic implementation in Verilog HDL.
Testing the various interfaces like SPI, XAUI, 10GbaseKR, PCIe etc.
Signal Integrity check for high speed signals using SI tools.
Summer internship Samsung Research Institute, Delhi May- July 2013
Was a part of the SDF team of the Application group at Samsung Research Institute (SRI), Noida.
Developed basic apps for Samsung smart tv and was in the defect review and discussion board sections of the team.
Projects
Data Compression
Semester Project
July-November 2011
Developed software in C to compress a given text file.
Huffman algorithm was implemented to achieve about 50% compression.
Dynamic Voltage Scaling B.Tech Project August 2013 –May 2014
Worked on DVS Techniques to reduce power dissipation. Razor technique was applied on 32 bit full adder for error detection when optimizing power consumption with voltage scaling. Application of such technique on DSP systems where some error is tolerable was studied.
Achievements / Extra Curricular Activities
Senior member of Student Mentorship Cell(SMC)-IIT(BHU), Varanasi.
Mentor and Organizer of DigiLock and Analock, the digital and analog technical contests involving FPGA based solutions as a part of AAYAM, technical departmental festival.
Qualified semi-finals in I-ROBOT, line following robot competition in TECHNEX’11 (annual technical festival of IIT(BHU). Successfully implemented an interface between microcontroller and IR sensors.
Personal Information
Father: P.V.Ramana Reddy
Mother: P.Rajeswari
Gender: Male
Date of Birth: 16/06/1992
Nationality: Indian
Languages: English, Telugu, Hindi.
Address: H.No:29/274,Tekke,Nandyal,Kurnool District, Andhra Pradesh, 518501.
