Ehab Mostafa

Ehab Mostafa Farghly Education: • • • • • Faculty of Engineering – Cairo University Electronics and Electrical Communications Department Year of graduation: 2023 Overall grade: Very good with honors (82.6%) Graduation project grade: Excellent Software Skills: • • • Verilog/ SystemVerilog OOP / Data Structures Synopsys tools • • • Python • • Linux • C / C++ Bash Scripting MATLAB TCL/ Perl Experience: 1. CAD Design Engineer MaBrains — Feb 2025 – Nov 2025 Responsibilies: • • • • • Design and implement analog layout structures. Verify and fix layout issues using DRC and LVS checks. Writing DRC and LVS rules in Klayout and Calibre. Review and validate test patterns used in DRC and LVS rule development. Use Python in creation of Test patterns. 2. Analog Layout Internship under supervision Si-Vision Academy SI-Vision — Sep 2024 – Dec 2024 • • • • • Analog Basics, IC Fabrication Process and Matching Techniques Layout Dependent Effects and Short Channel Effects Parasitics , Noise, Isolation Techniques, ESD and Latch-up Layout Flow (Floorplanning, Routing, PEX, Physical Verification) Practicing in Synopsys tools (custom compiler) 3. Q4E Internship DD&DI Track under supervision Si-Vision SI-Vision — Dec 2023 – Jul 2024 • • • • • • Advanced Digital Design using Verilog and SystemVerilog CDC, RDC, DFT and UPF Power Aware Design RTL linting and FPGA prototyping Synthesis and Formality Placement and Routing Flow (Floorplanning, Placement, CTS, Routing) EMIR, Chip finishing and On Chip Variation Tools: Verdi, Spyglass, Design Compiler, Vivado, Formality, ICC2, Prime time 4. Digital IC Design Track ITI — Jul 2023 – Oct 2023 • • • Advanced Digital Design using Verilog and VHDL Learning C++ and OOP Learning ASIC Flow and FPGA Prototyping Courses: 1. 2. 3. 4. 5. ASIC Diploma at NajahNow under supervision of Eng. Islam Samir Digital IC Design Diploma Under supervision of Eng. Ali El-Temsah SolveNet: IC Compiler II: Block Level Implementation Udemy: Python OOP : Object Oriented Programming in Python Udemy: Python Programming Bootcamp (2019) (Feb-2023, May-2023) (Feb-2022, Jun-2022) (Online May-2024) (Online Jun-2024) (Online Jun-2024) Digital IC Design Projects: 1. Graduation project: Digital Implementation of ZigBee Transceiver with SI-VISION • Description: Design a ZigBee Transmitter and receiver which follows the IEEE standard for Low-Rate Wireless Networks, creating a high-level model for the transmitter, channel model, and receiver and writing an RTL for each function block and testing it using bit matching against its counter golden model. • Project phases: Design a system model using MATLAB following the IEEE standard: - TX Model (forming PPDU, O-QPSK modulation, Pulse shaping). - Channel Model (AWGN + Frequency and Phase offset). - Rx Model (Frequency and Phase offset estimation and correction, Matched filter, packet detection and synchronization, Symbol correction). - Conducted performance analysis and optimized design parameters to meet requirements. - Implementing the Tx, Rx, and a synthesizable channel model on an FPGA to test the final design Performance against the golden performance from the high-level model 2. Single-Cycle 32-bit RISC-V Processor 3. RTL to GDS Implementation of Low Power Configurable Multi Clock Digital System GITHUB Repo GITHUB Repo Layout Design Projects: • Final Project of SI-Vision Internship: fully differential Variable Gain Amplifier (VGA) - Provide the Complete floorplan of the VGA Layout. - Determine the suitable matching pattern Current mirrors and Diff Pairs. - Integrate the VGA with the Higher system. - Check LVS/DRC of the whole system. Verification Design Projects 1. Bank ATM design & Environment verification GITHUB Repo - The project aims to implement the core of the bank ATM design and make verification for it. - Digital Verification by implementing UVM environment: - Developed SVA assertions and coverage models, including statement, branch, and FSM coverage. Scripting Projects 1. Python Script Development for Automated Testbench Generation 2. TCL Script Development for Cell Propagation Delay Calculation GITHUB Repo GITHUB Repo