Bojan Jovanovic

 Jovanović Bojan University of Niš • Faculty of Electronic Engineering • - •-Date of birth:- • Citizenship: Serbian • IEEE Member Research interest Hybrid Magnetic Tunnel Junction (MTJ)-based memory cells and computing architectures, design of embedded/real-time/SoCs based on a programmable logic devices, power estimation and minimization techniques Education PhD in Electrical Engineering and Computer Science- Faculty of Electronic Engineering, University of Niš, Serbia Title: Analytical model for dynamic power estimation of arithmetic circuits implemented in FPGAs BSc in Electrical&Electronics Engineering- Faculty of Electronic Engineering, University of Niš, Serbia Title: An implementation of the breadth-first search algorithm on a chip GPA 9.30 out of 10 Technical skills IC design Cadence tools (Spectre, MDL, Virtuoso, RTL Compiler, EDI), Synopsis DC Programming VHDL, Verilog, Matlab, LabVIEW, C/C++, Perl, Java(basics) OS MS-Windows, Linux, Android Software QuartusII, Xilinx ISE, Altium, Eagle, MSOffice, LaTeX Language English (upper intermediate), French (intermediate, DELF B1 diploma) Work experience Postdoctoral research- LIRMM laboratory, Montpellier, France Research on hybrid (volatile/non-volatile), MTJ-based memory cells Tape-out of a hybrid (MTJ/MOS) memory chip in 28 nm FD-SOI technology Teaching and research assistant Faculty of Electronic Engineering, University of Niš, Serbia Lecturing and counseling students in Digital Electronics course Realized a new laboratory exercises based on the Altera DE1 board Written a student’s manual for Digital Electronics laboratory 2008-Present Research intern Technical University of Madrid, Integrated Systems Laboratory High-level power estimation of DSP circuits implemented in FPGAs 2010 Research and Development R&D Center Sentronis AD, Niš, Serbia Development of the electronic devices for magnetic field measurement Hall effect based electrical current measurement Automation of the magnetic sensor calibration process using LabVIEW Development of the digital part for 3-axis Hall Teslameter- publications Book chapters [1] B. Jovanovic, R. M. Brum, L. Torres (2015). Logic circuits design based on MRAM, from single to multi-states cells storage. In W. Zhao, G. Prenat (Eds.), Spintronic-based Computing, (pp. 179-200). Switzerland: Springer International Publishing, Link [2] R. M. Brum, B. Jovanovic, L. Torres (2015). Spintronic-Memory-Based Reconfigurable Computing. In P. E. Gaillardon (Ed), Reconfigurable Logic: Architecture, Tools, and Applications, (pp. 433-458), CRC Press, Link  Journal papers [1] B. Jovanovic, R. M. Brum, L. Torres, “Evaluation of hybrid MRAM/CMOS cells for "normally-off and instant-on" computing,” Analog Integrated Circuits and Signal Processing, vol. 81, no. 3, pp. 607-621, Oct. 2014. Link [2] B. Jovanovic, R. M. Brum, L. Torres, “Comparative Analysis of MTJ/CMOS Hybrid Cells based on TAS and In-plane STT Magnetic Tunnel Junctions,” IEEE Transactions on Magnetics, vol. 51, no. 2, Aug. 2014. Link, Cover Figure. [3] B. Jovanovic, R. M. Brum, L. Torres, “A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design,” Journal of Applied Physics, vol. 115, no. 13, p. 134316, Apr. 2014. Link [4] B. Jovanovic, R. Jevtic, C. Carreras, “Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits,” IEEE Transactions on Industrial Informatics, vol. 10, no. 1. pp. 393-398, Feb. 2014. Link [5] B. Jovanovic, M. Jevtic, “Methods for Power Minimization in Modern VLSI Circuits,” Int. J. Reasoning-based Intelligent Systems, vol. 4, nos. 1/2, pp. 46-57, Apr. 2012. Link [6] B. Jovanovic, M. Jevtic “FPGA implementation of a hybrid on-line process monitoring in PC based Real-Time systems,” Serbian J. of Electrical Engineering, vol. 8, no. 1, pp. 37-51, Jun. 2011. Link [7] N. Stamenkovic, B. Jovanovic, “Reverse Conversion Design for the 4-Moduli Set {2n-1,2n,2n+1, 22n+1-1},” Sci. J. Facta Universitatis, ser:Elec.Energ., vol. 24, no. 1, pp. 89-103, Apr. 2011. Link [8] B. Jovanovic, R. Jevtic and C. Carreras, “Triple-bit method for power estimation of nonlinear digital circuits in FPGAs,” Electronics Letters, vol. 46, no. 13, pp. 903-905, Jun. 2010. Link Some selected Conference papers [1] B. Jovanovic, R. Jevtic, C. Carreras, “TBT Signal Model for Improved Accuracy of High-level Dynamic Power Estimation Procedure,” In. Proc. of Small Systems Simulation Symposium, Niš, Serbia, 2012, pp. 62-66. [2] B. Jovanovic, M. Jevtic, “Optimization of the Binary Adder Architectures Implemented in ASICs and FPGAs,” In Proc. of 5th Int. Workshop on Soft Computing Applications, Szeged, Hungary, 2012, pp. 295-308. [3] R. Jevtic, B. Jovanovic, C. Carreras, “Power estimation of dividers implemented in FPGAs,” In Proc. of 21st Great Lakes Symposium on VLSI, Lausanne, Switzerland, 2011, pp. 313-318. [4] B. Jovanovic, M. Jevtic, “Total Power Consumption in Modern VLSI Circuits,” In. Proc. of Int. Conf. on ICEST, Niš, Serbia, 2011 (best paper award in Electronics section) [5] B. Jovanovic, M. Jevtic, “FPGA implementation of the hybrid on-line monitoring system for PC based RTS,” In Proc. of 53rd Conference for ETRAN, Donji Milanovac, Serbia, 2010, pp. EL4.4-1-4 (best paper award in Electronics section) [6] B. Jovanovic, M. Jevtic, “One implementation of a Hybrid On-line process monitoring in PC based Real-Time Systems,” In Proc. of Conf. on Embedded Real-Time Software and Systems, Toulouse, France, 2010, pp. 7D-3 1-8 references Name: Lionel Torres Carlos Carreras Ruzica Jevtic Title: Full Professor Associate Professor Postdoc Researcher Organization: University of Montpellier 2/ CNRS Technical University of Madrid Berkeley Wireless Research center e-mail:--- Telephone: (- (- ext. 4218 (- Ref. Letter: Link Link Link