Ali Mahgoub

Ali Mahgoub ADDRESS Nasr City, Cairo, Egypt MOBILE (- E-MAIL- WORK EXPERIENCE: Senior Hardware engineer at Mentor Graphics Egypt from September 2017 to February 2018. Hardware engineer at Mentor Graphics Egypt from February 2016 to September 2017. Digital verification IPs implementation of serial communication PHYs and Protocols with the following responsibilities:  Analyze the PHYs and Protocols standards and extract the required specification to implement them  Design architect, RTL coding, debug and fix any reported issue by the verification team  Run linting and CDC formal analysis check on the design  Document all the design details  Support the customers Digital design engineer at Wasiela-Egypt from October 2011 to February 2016. Verilog and VHDL implementation of various digital blocks in the physical layer of different telecommunication standards and customized transceivers with the following responsibilities:  Understand the standard and the system model of the block required to be implemented, analyze the block and find a suitable architecture for the design  RTL coding using Verilog or VHDL with functional simulation for the designed block  FPGA synthesis, static timing analysis, optimization and gate level simulation  Document the design Digital design engineer at CarrierComm-USA by Wasiela-Egypt from November 2014 to May 2015.  Hardware implementation and verification of AES Encryption and Decryption modules wrappers for SC modem  Write, run and debug tests of the top level SC transceiver includes frame constructor, AES, protection and aggregation, NCO and rate adaptation designs with their MAC interface using an existing UVM testing environment PROJECTS: Work experience: Involved in the design and verification of Emulation Platform, FPGA and ASIC projects for serial and wireless communication systems that based mainly on OFDM transmission. 1. DFI Null PHY (Based on Veloce Emulator): 2. 3. 4.  Re-architect, design and implementation USB V3.1 Null PHY (Based on Veloce Emulator):  Full design and implementation MIPI UniPro V1.6 (Based on Veloce Emulator):  Developed multi clock domains version of an existing IP  Debugged and fixed issues MIPI M-PHY V4.0 PHY (Based on Veloce Emulator):  Debugged and fixed issues of an existing IP 5. DVB-C (Based on FPGA):  Functional verification of the full receiver  Participated in creating and developing offline and online test environment and running a DEMO for the receiver on a Terasic board 6. LTE (Based on FPGA):  Design and implementation of PSS FIR digital filter with transpose structure  Design and implementation of FFO estimation block 7. OFDM application specific nonstandard transceiver (Based on ASIC):  Design and implementation of encryption and decryption for NIST AES-128/192/256  Design and implementation of phase noise estimation and compensation  Integration, controller implementation and verification for part of the receiver that includes: FFT shift, residual SFO and CFO estimation, phase noise estimation and compensation, channel equalization, transmit IQ compensation, SISO demapper and KBest MIMO  Integration for the uplink transmitter and receiver with impairments (SFO, CFO, noise, channel, Tx and Rx IQ errors) using C code and verifying it against MATLAB  Support and generate test cases for NCO and DPLL 8. SC application specific nonstandard transceiver (Based on ASIC): Design and implementation of:  EVM  IQ imbalance compensation  Pilots extraction and processing Miscellaneous: Design and implementation of:  Generic FIR digital filters with direct form and transpose structures for fixed and nonfixed coefficients  Clock gating according to Altera Standard Scheme  Generic single iteration of Newton-Raphson technique divider  Generic complex multipliers with different architectures  Cholesky decomposition technique and matrices multiplication  Generic ceil of log base 2, Generic floor of log base 2, Generic log base 2 using LUT and Generic log base 2 using iterative method Self-projects:  Design and implementation of modulation mapper for DBPSK,  BPSK, QPSK, 16QAM PUBLICATIONS & PATENTS:   A. M. Mansour, A. M. El-Sawy, M. S. Aziz, and A. T. Sayed, "A New Hardware Implementation of Base 2 Logarithm for FPGA," International Journal of Signal Processing Systems, Vol. 3, No. 2, pp. 177-182, December 2015. doi:-/ijsps- Mansour, A. , El-Sawy, A. , Sayed, A.. "A New Floating Point Implementation of Base 2 Logarithm". World Academy of Science, Engineering and Technology, International Science Index 94, International Journal of Mathematical, Computational, Natural and Physical Engineering (2014), 8(10), 1310 - 1313 EDUCATION:  July 2011, Faculty of Engineering, Ain Shams University, Cairo, Egypt.  Major: Electronics and Communication Engineering  Accumulative grade: Very good  Graduation project: Simulation of LTE-MIMO physical layer using MATLAB, sponsored by SYSTEL Egypt  Graduation project grade: Excellent TRAINING COURSES AND CERTIFICATIONS:  October 2011 - November 2012, Finished levels 3-8 of the conversation English course a Berlitz language center   March-July 2011, VHDL course August 2010, CCNA course COMPUTER SKILLS:          Hardware modeling using Verilog, VHDL and System Verilog FPGA and ASIC design flow EDA tools: MentorGraphics-QuestaSim, MentorGraphics-Questa Formal Verification, MentorGrapchis-Veloce, Altera suite (Quartus, SOPC builder and Nios IDE), Xilinx-ISE, Xilinx-Vivado, Synopsys-DC, and Cadenece (NCSIM and SimVision) Fixed point numbers Programming languages: C and MATLAB Revision control systems: SVN, GIT, CVS and Mercurial Scripting languages: Shell, Tcl and Make files Documentation skills using Latex Good experience in using Linux operating system LANGUAGES:   Arabic: Native language English: Very good command written and spoken PERSONAL:     Date of Birth: February 8, 1990 Nationality: Egyptian Marital Status: Single Military Status: Exempted